`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:25:14 09/12/2012 
// Design Name: 
// Module Name:    Divider 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Divider (
 clk_i ,rst_i,
 clk1hz_o 
  );
  //499999
  //126499
 input clk_i,rst_i;
 output clk1hz_o;
 reg clk1hz_o;
 reg [15:0] counter_out ;
 
 initial begin
	counter_out=0;
	clk1hz_o=0;
 end
   always @(posedge clk_i)
		begin
			if(rst_i)
				begin	
					clk1hz_o <= 0; 
					counter_out <= 0;
				end	
			else 
				begin
				if(counter_out==10)
						begin
							clk1hz_o<=~clk1hz_o;
							counter_out <= 0;
						end
					else
						begin
							counter_out <= counter_out + 1;
						end
				end
			end					
 endmodule 
